Embodiments of the present invention relate to an array substrate and a display device comprising the array substrate.
Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) have the advantages of small volume, low power consumption, irradiation-free, etc., and thus have prevailed in the current flat panel display market.
Generally, a display area on a substrate of a TFT-LCD contains a plurality of pixel units, each of the plurality of pixel units is a rectangular region formed by crossing of two gate lines and two data lines, and a TFT and a pixel electrode are provided within each of the plurality of pixel units. For each TFT, its gate electrode and source/drain electrode are collected to a gate line and a data line, respectively, all the gate lines are collected to a gate driver, and all the data lines are connected a source/drain driver, so as to provide driving signals for the gate electrode and the source/drain electrode of the TFT.
Because the cost of a source/drain driving integrated circuit (IC) chip is higher than the cost of a gate driving IC chip, a conventional wiring technology (in which the number of driving IC chips corresponds to the number of leading wires) makes manufacturing cost of the LCD higher. In order to overcome this defect, a Dual Gate technology emerges, namely, an effect of reducing the number of the data lines (corresponding to the number of the source driving IC chips) by half is achieved by doubling the number of gate leading wires (corresponding to the number of the gate driving IC chips). Thereby, the data lines can be reduced, so as to decrease the manufacturing cost of the LCD. As shown in FIG. 1, on an array substrate in which the Dual Gate technology is used, there are included first gate lines G1, G3 and G5 parallel to each other and second gate lines G2, G4 and G6 parallel to each other, and data lines are insulated from and cross perpendicularly over the first gate lines and the second gate lines. Two columns of pixel units are contained between two adjacent data lines, and TFTs for the two columns of pixel units are connected to one of the first gate lines and one of the second gate lines, respectively. For example, a TFT 12A for a pixel unit in which a pixel electrode 10A is located is connected to the first gate line G1, a TFT 12B for a pixel unit in which a pixel electrode 10B is located is connected to the second gate line G2. The first gate lines G1, G3 and G5 are extracted from the left side of the substrate, and the second gate lines G2, G4 and G6 are extracted from the right side of the substrate, and they are connected to a corresponding gate driver A and a corresponding gate driver B, respectively. The data lines are extracted from a side adjacent to the two gate drivers and are connected to a source driver. The gate drivers and the source driver are controlled by a timing controller (T-con) to transmit a signal to a corresponding pixel electrode.
For a conventional single-gate-line pixel structure, the coupling capacitance between a data line and a pixel electrode is inversely proportional to the distance between the data line and the pixel electrode, and if the aligning precision is very high and distances from the pixel unit to adjacent two data lines thereof are equal to one another at ideal conditions, coupling capacitances for each pixel unit are equal to one another. In a practical process, the aligning deviation occurs between a pixel electrode layer and a data line layer, the coupling capacitance may increase or reduce with the reduction or increase of the distance. Nevertheless, for each of the pixel units, because there are two data lines on both sides thereof, when the aligning deviation occurs, the coupling capacitance between the pixel unit and one of the two data lines increases and the coupling capacitance between the pixel unit and the other reduces accordingly, the positive addition and the negative addition may offset to each other and so their effects may offset after the two coupling capacitances are added. And, the deviation is the same for each of the pixel units. However, regarding a Dual-Gate pixel structure, as shown in FIG. 2(a), for each of the pixel electrodes, the coupling capacitance generates between only one of the data lines and the pixel electrode, for example, what corresponds to a pixel electrode A is Cpd1, and what corresponds to a pixel electrode B is Cpd2. Distance between the pixel electrode A and its adjacent data line is d1, and distance between the pixel electrode B and its adjacent data line is d2. As shown in FIG. 2(b), in a practical process, when the aligning deviation occurs between the pixel electrode layer and the data line layer, the deviation results in such a case that d1 is reduced and Cpd1 is increased and d2 is increased and Cpd2 is reduced. Therefore, impacts on two adjacent pixel electrodes which are exerted by data lines are imbalanced. Thereby, the display effect of the LCD is affected.
Similarly, in such a case that the data lines and the pixel electrodes are not arranged alternately, impacts on two adjacent pixel electrodes which are exerted by the data lines are imbalanced. Thus, the aligning deviation between the pixel electrode layer and the data line layer in the practical process may exert the negative influence on the display effect of the LCD.
On a conventional array substrate of a TFT-LCD, a side leading wire manner is used for the gate electrode, the gate leading wires are provided at two opposed sides of an active pixel region of the TFT-LCD, and thus scan signals which are outputted from an gate driver are transmitted to scan lines in the pixel region to thereby control each of the pixel units. However, each of the gate leading wires occupies a certain area, and hence an adequate peripheral wiring region (fan-out) needs to be reserved previously so as to arrange all of the gate leading wires. The size of the fan-out region determines the size of a frame of the substrate of the TFT-LCD, and the size of the fan-out region is determined by the number of the gate leading wires, that is, the resolution of the TFT-LCD determines the size of the frame. Here, the gate leading wire refers to a wire for connecting a gate line to the gate driver.
In the prior art, in order to decrease the size of the frame of the TFT-LCD, a peripheral double-layered wiring (dual fan-out) design is used, in which two kinds of metal are used for wirings in different layers in the fan-out, and a Gate-layer metal and a Source-Drain-layer (SD-layer) metal are usually selected for wirings in a Gate-layer and a SD-layer, respectively. By this way, the number of leading wire for each layer is reduced by half, and the area occupied by the wiring region is decreased accordingly, whereby the size of the frame can be reduced. As the resolution of the LCD becomes larger and larger, the size of the frame will also become larger and larger. Even if the size of the frame can be decreased by using the Dual fan-out design, the resolution of the LCD still restricts the size of the frame to thereby hinder the development of a large-scale, thin-frame LCD.